The present invention relates to electronic circuits, and more particularly, to techniques for selecting phases of clock signals.
The Stratix® III field programmable gate array (FPGA) manufactured by Altera Corporation of San Jose, Calif., contained the circuitry shown in FIG. 2A of the present application, which operated according to the signal timing shown in FIG. 2C of the present application. The Stratix III FPGA was sold in August of 2007.
Phase-locked loops (PLLs) are an essential building block of many integrated circuits, providing periodic signals for data recovery, data transfer, and other clocking functions. PLLs often supply a clock signal to one or more counters or dividers that divide a signal from an oscillator to a lower frequency clock signal for distribution around an integrated circuit or system. PLLs can have a voltage controlled oscillator, a current controlled oscillator, or a digitally controlled oscillator.
A programmable logic integrated circuit (IC), such as a field programmable gate array (FPGA) or a programmable logic device (PLD), typically contains programmable logic circuit blocks that can be configured to perform a variety of functions. Some programmable ICs also include PLLs that have configurable settings.
When used inside a programmable logic IC, a PLL can have many configurations. Each configuration defines a specific application use in the user mode of the programmable logic IC. The requirements for input and output frequency, bandwidth, phase relationship, jitter budget, and many other feature requirements trigger a unique configuration for a PLL.
After a FPGA chip has been programmed, and a different configuration is needed, a new configuration is loaded into the chip. Loading a new configuration forces the chip to go out of user mode. As a result, the functionality of the system gets disrupted.